Receivers for electronic communication systems require adaptive timing recovery loops to derive a receiver sampling clock that is used to minimize the receive signal error. As part of this process, the receive-clock must compensate for the frequency offset between the far end transmitter and the local reference clock. Typically, the frequency offset is in the range of a few hundred parts per million (PPM), such that the receiver clock frequency must be adjusted to a very low rate relative to the actual frequency of the clock. Traditionally, this is done by using a receive phase locked loop (PLL) with a voltage controlled oscillator (VCO), where the VCO frequency can be accurately trimmed by small variations in a control voltage.
In general, since the receiver must adapt to the errors in both phase and frequency, a 2nd order timing recovery loop is required. In addition, many systems require extremely low receiver phase error, also known as jitter, to minimize the receiver signal to noise ratio (SNR) degradation due to crosstalk and other high-pass type impairments. In analog timing recovery systems, where the main pole is realized with a voltage controlled oscillator (VCO) or a voltage controlled crystal oscillator (VCXO), improvements in oscillator technology have helped to reduce the inherent phase noise in such systems. In a digital timing recovery system, where the pole is often realized with a numerically controlled oscillator (NCO), low jitter can be achieved by decreasing the step size in the NCO (e.g. lowering it's gain), and by limiting the rate and size of updates to the NCO.
FIG. 1 shows a typical timing recovery loop 100 having a timing error detector 102, a loop filter 104, a controller 106 and a numerically controlled oscillator (NCO) 108. Here, the NCO 108 is realized by a phase accumulator (not shown), which has the transfer function:H(z)=(1/N)×[1/(1−z−1)],and an address generator (not shown) configured such that the output phase is a linear function of the input address. The controller 106 is used to transform the loop filter output 110 into a specific address for the NCO 108, where the loop filter input 112 is results from the output of the timing error detector 102.
FIG. 2 shows a typical loop filter 104 having a digital integrator 200, three multipliers 202a, 202b, and 202c having unique gain values a, b and c, respectively, where gain value a is the gain of the multiplier 202a in the linear path, gain value b is the gain of the multiplier 202b in the integration path and gain value is the gain of the multiplier 202c after the output of the unit delay element 206 and before the second summing node 200. An accumulator 204 is configured as a proportional+integral filter. When used in a loop 100 shown in FIG. 1, the unit delay element 206 of the structure 104 is a linear combination of the instantaneous phase error 110 having an output:y(z)=(b+a)−(a×c×z−1)/[1−(c×z−1)],such that the value Y(z) (referred to as 110 in FIG. 2) typically has a wide dynamic range. In order to minimize jitter, it is desirable to minimize the difference between successive output phases, thus the NCO 108 is designed to be driven by a low-precision input signal that simply increments or decrements the output phase by the step size of the (stepped) NCO 206, that is:Phase step size˜(1/n),orphase(n)=phase(n−1)+(U)×phase step,where U is a singed integer scale factor.
Typically the operation of translating the wide dynamic range phase error estimate 110 into a sequence of increment/decrement pulses for the NCO 108 is performed by some pulse width modulation technique such as a slope intersect method, a delta method or a sigma-delta method.
Alternative timing recovery architectures that employ delay locked loops (DLL) can also be employed for this operation. However, because such circuits use delay lines of phase interpolators rather than VCO's, in such a manner that the frequency of the main reference clock dose not need to be changed, such systems require additional circuitry to control the receive clock frequency.
Accordingly, what is needed is a method to digitally control the timing recovery to minimize (and control) jitter in the recovered clock, with reduced word-length requirements and does not require additional circuitry to control the receive clock frequency.